Convert specification
to silicon

Coresmith is an agentic system that converts chip specifications into silicon. The LangGraph pipeline drives the full ASIC flow — architecture, RTL, verification, synthesis, place-and-route, DRC, LVS — to a signed-off Sky130 GDS-II.

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coresmith

promptuser

>Create an intra-only, luma-only video compression ASIC in the 130nm node.

Waveform

residual in5-stage pipeqcoeff outcyc 04 / 27

01 · the loop

Three state machines.
One conversation.

Coresmith runs in three stages: architecture, frontend design, and backend design. Dozens of agents are defined in LangGraph, the dependencies between them (RTL bug, timing closure) are triaged by Coresmith. Blockers are escalated to you.

architecture

pass

fail

retry

orchestrator/langgraph/architecture_graph.py

start

Gather Requirements

Design Lead (AI)

PRD specialist. Phase 1: emits sizing questions to the architect. Phase 2 (after answers): drafts the full Product Requirements Document.

Escalate PRD

You

Interrupt-based human gate. Pauses the graph and surfaces the PRD sizing questions for the architect to answer.

interrupt()

System Architecture

Design Lead (AI)

Generates the System Architecture Document (SAD): HW/FW/SW partitioning, system flows, technology rationale, and architecture decisions with rationale.

Functional Requirements

Design Lead (AI)

Generates the Functional Requirements Document (FRD) from PRD + SAD — quantitative, measurable, testable requirements with acceptance criteria.

Block Diagram

Design Lead (AI)

LLM specialist generates or refines the block diagram from requirements, PDK summary, target clock, prior constraint feedback, and any human edits.

Escalate Diagram

You

Human gate. Fires when the block-diagram specialist emits clarifying questions or returns zero blocks.

interrupt()

Memory Map

Design Lead (AI)

LLM specialist derives the system memory map from the block diagram, target clock, and ERS — addresses, peripheral count, regions.

Clock Tree

Design Lead (AI)

LLM specialist plans the clock-domain topology from the block diagram and target clock — clock domains and crossings.

Register Spec

Design Lead (AI)

LLM specialist produces the per-block register specification driven by the block diagram and memory map.

Constraint Check

Design Lead (AI)

LLM constraint specialist checks the full set against PDK + benchmarks. Returns violations tagged structural (need human) vs. auto-fixable (LLM can iterate).

Escalate Constraints

You

Human gate for structural violations the LLM cannot self-fix. Architect can retry, accept the violation, or abort.

interrupt()

Constraint Iteration

Build System (AI)

Bumps the round counter; routes back to Block Diagram for an auto-fix attempt unless the per-run round limit has been hit.

Escalate Exhausted

You

Human gate after max_rounds × 3 hard ceiling. Architect can accept the partial result, retry once more, or abort.

interrupt()

Finalize Architecture

Build System (AI)

Persists the architecture decisions to state and writes block_specs.json so the frontend pipeline has a contract to consume.

Create Documentation

Build System (AI)

Generates a ReactFlow-compatible block-diagram visualization, the final ERS document, and a self-contained HTML dashboard with PRD/SAD/FRD/ERS/memory/clocks.

Final Review

You

OK2DEV gate. Architect reviews the full architecture package and approves, revises (back to Block Diagram), or aborts.

interrupt()

Architecture Complete

Build System (AI)

Marks the run as successful. The frontend pipeline picks up block_specs.json from here.

Abort

Build System (AI)

User-initiated termination from any escalation gate.

end

20 nodes · 10 forward edges · 23 conditional / loop

RTL Engineer (AI)

Verification Engineer (AI)

PD Lead (AI)

Design Lead (AI)

Build System (AI)

You

02 · how it works

You have the specification.
Coresmith builds the prototype.

Chip design used to need a team of specialists and a year of elapsed time. Coresmith compresses that into a single agent loop, with the human in the loop only for direction — not for waiting on tools.

step 01
Start Coresmith through Claude or Codex
Coresmith is a persistent daemon that orchestrates the agents driving your ASIC flow. You interact with Coresmith through Claude Code or Codex CLI. Coresmith is bootstrapped with a Skill file.
$ coresmith daemon start --project-root ./my-asic
step 02
Approve the architecture
Block diagram, memory map, clock tree and register spec land in your review. One human gate — OK2DEV — before any RTL gets written.
$ coresmith architecture start --requirements requirements.md
step 03
Let the loop run
RTL is generated, linted, simulated, synthesized, placed, routed. On any failure the agent reads its own tool logs, diagnoses, and retries with corrective constraints.
$ coresmith run start --blocks-file blocks.yaml
step 04
Sign off and tape out
DRC clean, LVS match, timing closed. A GDS-II is generated, ready for a MPW like TinyTapeout.com.
$ coresmith resume --action approve

03 · hero use case

MJPEG image codec,
agent-built end‑to‑end.

From a one-paragraph spec, Coresmith’s agents produced a 12-block intra-only luma soft IP — fp16 DCT, quantization, zig-zag scan, entropy coding, deblocking — plus an integration top that decodes a real 1024 × 1024 frame. The same byte stream is replayable in Python and through the generated Verilog.

rate-distortion · 54-frame mort sweepv10 sweep

Apple M4 CodecCoresmith chip

MJPEG frame reconstruction at QP 24 — psnr
41.45 dB
bpp
2.904
size
372 KB

MJPEG frame reconstruction at QP 36 — psnr
34.21 dB
bpp
1.118
size
143 KB

MJPEG frame reconstruction at QP 48 — psnr
27.83 dB
bpp
0.336
size
43.1 KB

verilator · generated chip_tophardware proof

The image on the right was simulated through the final netlist generated by Coresmith. It approached the golden reference model within 1.15 dB.

psnr: 39.85 dB
vs golden: +1.15 dB
codec: MJPEG

04 · the stack

Open source
or bring your own EDA tools.

Coresmith uses Claude or Codex for reasoning and the open Yosys / OpenROAD / Magic stack for quick iterations.

Claude/ LLM backbone

LangGraph/ orchestration

Verilator/ lint · sim

cocotb/ testbenches

Yosys/ synthesis

OpenROAD/ place & route

Magic/ DRC

netgen/ LVS

OpenSTA/ static timing

KLayout/ GDS · viewer

Sky130 PDK/ SkyWater 130nm

OpenTelemetry/ tracing

Claude/ LLM backbone

LangGraph/ orchestration

Verilator/ lint · sim

cocotb/ testbenches

Yosys/ synthesis

OpenROAD/ place & route

Magic/ DRC

netgen/ LVS

OpenSTA/ static timing

KLayout/ GDS · viewer

Sky130 PDK/ SkyWater 130nm

OpenTelemetry/ tracing

agent

Claude

LLM backbone

agent

LangGraph

orchestration

frontend

Verilator

lint · sim

frontend

cocotb

testbenches

frontend

Yosys

synthesis

backend

OpenROAD

place & route

backend

Magic

DRC

backend

netgen

LVS

backend

OpenSTA

static timing

signoff

KLayout

GDS · viewer

pdk

Sky130 PDK

SkyWater 130nm

infra

OpenTelemetry

tracing

Convert specificationto silicon.

Three state machines. One conversation.

You have the specification.Coresmith builds the prototype.

Start Coresmith through Claude or Codex

Approve the architecture

Let the loop run

Sign off and tape out

MJPEG image codec,agent-built end‑to‑end.

Open sourceor bring your own EDA tools.

Convert specification
to silicon

Three state machines.
One conversation.

You have the specification.
Coresmith builds the prototype.

MJPEG image codec,
agent-built end‑to‑end.

Open source
or bring your own EDA tools.